Power converters offer the ability to convert between different forms of electrical power, including from a direct current (DC) voltage at, say, 48 V to a DC voltage suitable for integrated electronics, e.g., 1.8 V. A variety of power converter designs are known and used, including the “current doubler” design shown in FIG. 1A, which offers an economical implementation with relatively high operating efficiency.
The design of FIG. 1A includes a primary switch array 101 in the form of a half bridge that alternately closes (turns “on”) n-channel power MOSFETs P1 and P2 to convert the input DC voltage Vin into an alternating voltage Vp across the transformer primary. Capacitors C1 and C2 provide charge storage and close the current path through the transformer primary. (Parasitic inductances Lm and Lp are shown here to represent the magnetizing inductance and leakage inductance of the transformer core, respectively, and are included here for design evaluation purposes. However, with respect to the inventive embodiments disclosed herein below, it is contemplated that these inductance values may be deliberately adjusted via customization of the transformer design and/or augmented with discrete inductors to extend the operating range and to improve efficiency performance characteristics of the converter.)
Transformer T is a step-down transformer, meaning that the current flow in the transformer secondary is a magnified version of the current flow in the transformer primary even as the secondary voltage Vs is reduced by the same factor. The secondary current direction alternates in response to the alternation of the primary voltage Vp. In the secondary switch array, n-channel power MOSFETs S1 and S2 are turned “on” by default, connecting the drive terminals of inductors Ls1 and Ls2 to ground and thereby enabling any ongoing current flow through the inductors to continue charging the output capacitor Co via their common connection terminal. Transistor S1 opens (turns “off”) while the secondary voltage Vs is positive, enabling Vs to boost the current flow through the drive terminal of inductor Ls1. Similarly transistor S2 opens while Vs is negative, enabling the current flow through the drive terminal of inductor Ls2 to be boosted. The current flows through inductors Ls1 and Ls2 can thereby be alternately boosted, thereby charging the output capacitor to an output voltage Vout (the difference between Voutp and Voutn). Current sensors generate current sense signals Is1 and Is2 that indicate the current flow through the inductors Ls1 and Ls2 respectively.
The design includes a controller 102 that generates switch control signals PWM_P1, PWM_P2, PWM_S1, PWM_S2, which may have digital logic levels. A gate driver 104 converts the switch control signals PWM_P1, PWM_P2 into gate signals for transistors P1 and P2, and gate driver 106 converts switch control signals PWM_S1, PWM_S2, into gate signals for transistors S1 and S2, respectively. (The transistors may require gate voltages well in excess of digital logic levels.)
Controller 102 generates the switch control signals in response to measurements of Vin, Vout (or, as illustrated, to Voutp and Voutn), Is1, and Is2. The controller includes a pulse-width-modulated (PWM) signal generator 107, which generates alternate pulses of the PWM_P1 and PWM_P2 switch control signals at a fixed frequency, but adjusts the width of the pulses as needed to regulate the output DC voltage Vout. (Note, however, that pulse widths are limited to at most 50% of the period, because P1 and P2 are not permitted to be closed at the same time.) Because the current sense signals Is1 and Is2 represent inductor-stored energy that is already enroute to the output capacitor, the generator 107 may employ them to increase stability and robustness of the feedback loop.
Inverters 108 cause the PWM_S1 and PWM_S2 switch control signals to be de-asserted when PWM_P1 and PWM_P2 are asserted, respectively, so that the energy applied to the transformer primary is suitably conveyed to inductor Ls1 or Ls2, respectively. Delay elements Ds introduce a small delay from the transitions of PWM_P1 and PWM_P2 to the transitions of PWM_S1 and PWM_S2. (Depending on design, the delay elements Ds may delay only upward transitions, downward transitions, or both types of transistions.) If set properly (e.g., by adaptive training), the delay elements enable soft-switching (e.g., zero-voltage switching (ZVS) or zero-current switching (ZCS)) of transistors S1 and S2, reducing switching-related power losses in the converter. Soft-switching techniques are well known to those in the art and need not be discussed in detail here.
FIG. 1B shows a current doubler design that includes a primary switch array 111 in the form of a full bridge to convert the input voltage Vin from a DC voltage to an alternating voltage Vp. The capacitors C1, C2 of FIG. 1A are replaced by n-channel power MOSFETs P3, P0. Transistors P1 and P0 are closed together to provide a forward current flow path through the transformer primary, and at alternate times transistors P2 and P3 are closed together to provide a reverse current flow path through the primary. A gate driver 114 converts the switch control signals into gate signals for transistors P0-P3, optionally including a phase shift (i.e., delay elements) to provide soft-switching for these transistors and thereby further reducing switching-related power losses in the converter. The secondary stage of the converter remains the same.
In both the half-bridge and full-bridge current doubler designs, the inductor currents are boosted alternately, and the boost rate is limited by the 50% maximum pulse width. This characteristic limits the converter's responsiveness to load transients. Further, in systems where reverse power transfer conditions may occur (e.g., a load release transient, or a fast controlled ramp-down), transistors S1 and S2 may have to sustain elevated voltages, necessitating the use of more expensive and potentially less-efficient components. It is desired to address these shortcomings without compromising the efficiency and economic advantages of a current doubler design.